DCC Design for the SDC Straw Tube Tracker

• Introduction

• Models and Simulation Results

• Preliminary ASIC Development

• Goals and Schedule Introduction

The straw tube DCC design is constrained by

• Noise on analogue FE caused by digital activity

• Space and power considerations

• Rad-hard requirements

Several groups involved in DCC architectural design and simulation

• SSCL group has been working on – High-level simulations of buffering strategies

– Noise issues on the Front End Board (FEB)

– Data transmission technologies from FEB

• Toronto/McGill group has been studying – Detailed simulations of a “straw man” design – Buffering from L1 → Crate Interface Card (CIC)

– Design of prototype ASIC’s for DCC on FEB

Straw DCC Architectural Studies

Design of the DCC system has assumed

• Each FEB will instrument ∼ 160 channels

• TMC will read out either 4 or 8 channels

• Crate Interface Card will handle 16-32 FEB

System Level Assumptions

• L1 accept rate ≤ 10−3

• L2 trigger rate ≤ 10 kHz

• occupancy/crossing/channel ≤ 0.05

• ≤ 3 crossings read out per trigger

DCC design avoids microprocessor on FEB

• Minimizes digital activity on FEB

• Consists of multiplexor (FMUX) and transmitter (FETX)

• Buffers and processors located on CIC

Simulation Studies

VERILOG simulation studies have been performed

• Evaluate FE chip buffer requirements

• Buffer and bandwidth requirements on FMUX/FETX • Requirements on CIC

Simulations have considered various issues

• Considered “event overlap”

• Physics correlations (min-bias and high pt collisions)

• Ordering of data by channel and trigger ID

• Latencies in L1 and L2 trigger

Overlap and Data Correlations

Probability of 2 L2 triggers sharing hits is small

Considered effects of regional data correlations

• Estimated using hits from full SDCSIM (Carleton U.)

• Considered different physical layout

Data Ordering and L2 Latencies

Data moves off FEB in channel and event order

• Considered several strategies – Spacing L2 accepts to ensure readout completes – FE chip provides control information

• L2 accept spacing as large as 50 μs tolerable

“L2 Latency” has modest impact on buffering Alternatively, have TMC generate “end-of-trigger” hit

• This control information also has modest impact

Prefer having control information

• Inherently more robust (error detection easier)

• More flexibility

CIC Buffering Studies

Have performed preliminary buffering studies on CIC

• Data from each FEB is pushed to CIC

• FEB→CIC bandwidth ≤ 4 Mbytes/s

• CIC coalesces event data into a single packet

CIC Input Buffer Occupancies CIC input buffer requirements is affected by

• CIC latency

• Bandwidth of CIC → DAQ system

Summary of Simulation Results

Results of simulation studies

Data buffering prior to L1 trigger  ≤ 18 hits
Data buffering prior to L2 trigger  8 hits
TMC readout rate  4 Mbit/s
FMUX Buffer size (4 channel TMC)  15 hits
FMUX→CIC bandwidth  4 Mbyte/s
CIC Input buffer size  400 hits
CIC Output buffer size  1000 hits
CIC Output bandwidth  40 Mbyte/s

Other Observations

• Data correlations have modest impact • L2 Accept latency can be 30 − 50 μs

FMUX Prototype Development

Noise on FEB is significant technical risk

• Minimize digital activity on FEB

• Avoid high speed digital transmission

• Controlled risetime of signals

• Employ low-level differential signals (±100mV?)

• Decouple analogue and digital components

Develop DCC design with minimal functionality on FEB

• Designing low-level differential receivers and drivers

• Simulated circuit designed by J. Van Der Spiegel

ASIC Development Schedule

First fabrication run of receiver will take place in July

• Use Northern Telecom 1.2 μ double-poly process

• Expect to use FPGA’s to implement prototype FMUX

• More complete FMUX prototype ASIC by end of the year

Also designing test board for prototype FMUX

• Employ Trigger Emulation Module for trigger, clock signals • Mezzanine architecture to allow tests of several circuits • Confronting issues of clock distribution, slow control

• Expect to have design complete by end of summer

Summary

• Preliminary simulation work on FEB now complete • Design of prototype ASIC’s in initial phase

• Prototype receivers / drivers September 92

• Prototype FMUX available by November 92