Front End Electronics and DAQ R&D

for SDC Straw Tracker and FCAL

A. Hölscher, P. Sinervo and G. Stairs University of Toronto K. Ragan and K. Strahl McGill University

• Introduction

• Data Collection Circuit for Straw Tubes – Design and Simulation Results

– Prototype ASIC Development

– Goals and Schedule

• FCAL Electronics Outer Tracker Electronics

OT essential for charged particle detection

• 140,000 4-mm diameter straw tubes

• arranged in 5 super layers (3 axial and 2 stereo)

• Instruments region between r = 0.8 and 1.6 m

The straw tube tracker electronics consists of:

• Amplifier-Shaper-Discriminator circuit (ASD)

• Time Memory Cell (TMC)—digitizes before L1 decision • Buffer to hold data prior to L2 decision (L2B)

• Data Collection Circuit (DCC)

• Interface to DAQ (Crate Interface Card or CIC)

Baseline places ASD/TMC/L2B/DCC inside solenoid

• Analogue and digital components must be isolated

• Need to optimize space and power consumption

• Must be rad-hard (∼ 1 MRad)

One option: Move electronics (except ASD’s) outside calorimeter

• Reduces radiation exposure, cooling problems

• More easily maintained

• But longer signal path between ASD and TMC

Has little impact on DCC functionality

Organization of Effort

Several groups involved in Outer Tracker FE

• University of Pennsylvania – Amplifier-Shaper-Discriminator (ASD)

– Packaging of Electronics and Cabling

– Architecture and Management

• KEK, Tokyo, Tsukuba – Time Memory Cell (TMC)

– Level 2 Buffer Chip (L2B)

– Microcrate design, cooling

– Trigger electronics

• Toronto/McGill – Data Collection Circuits in microcrates

– FE-DAQ interface – Crate Interface Cards (CIC)’s

Overview of IPP Effort

Conceptual design and modelling of DCC

• Optimised architecture of system

• Estimated bandwidths, buffering requirements

• Specified functionality of components

• Completed in summer 1992

Design of components in microcrate (FMUX/FETX)

• Schematic design of FMUX and FETX

• Evaluation of failure modes/redundancy

• Communications protocols

• Design (Nov 1992) being reviewed

Development of prototype FMUX/FETX

• Establish design capability (with help of CMC)

• Design of low-level (±150 mV) differential receiver/driver (submitted Jun 1992)

• First prototype FMUX submitted Sep 1992

• Testing and evaluation started Dec 1992

Assembly of Prototype SDC DAQ system

• Putting together SDC Portable DAQ (VME)

• Designing VME test board for prototype FMUX

• Waiting for Trigger Emulation Module (TEM) from Wisconsin

Architectural Studies

Design of the DCC system has assumed

• microcrate instruments single module (156-212 channels)

• TMC will read out 4 channels

• Crate Interface Card will handle 8 microcrates

System Level Assumptions

• L1 accept rate ≤ 10−3

• L2 trigger rate ≤ 10 kHz

• occupancy/crossing/channel ≤ 0.05

• ≤ 3 crossings read out per trigger

DCC design avoids microprocessor in microcrate

• Consists of multiplexor (FMUX) and transmitter (FETX)

• Minimizes digital activity inside μcrate

• Buffers and processors located on CIC

Modelling and Conceptual Design Studies

Developed VERILOG simulations of read-out system

• Evaluate FE electronics buffer requirements

• Buffer and bandwidth requirements for FMUX/FETX • Requirements for CIC

Simulations have considered various issues

• Considered “event overlap”

• Physics correlations (min-bias and high pt collisions)

• Ordering of data by channel and trigger ID

• Latencies in L1 and L2 trigger

Summary of Simulation Results

Results of simulation studies

Data buffering prior to L1 trigger  ≤ 18 hits
Data buffering prior to L2 trigger  8 hits
TMC readout rate  4 Mbit/s
FMUX Buffer size (4 channel TMC)  15 hits
FMUX→CIC bandwidth  4 Mbyte/s
CIC Input buffer size  400 hits
CIC Output buffer size  1000 hits
CIC Output bandwidth  40 Mbyte/s

Other Observations

• Data correlations have modest impact

• L2 Accept latency can be 30 − 50 μs

Data Collection Circuit Design

Have developed a detailed design of DCC system

• Matched to dataflow requirements

• Avoids need for intelligence in microcrates

• Fault-tolerant

Front End Multiplexor/Transmitter

FMUX/FETX collect and multiplex data from TMC/L2B

• Each FMUX reads out 8 TMC/L2B (32 channels)

• Data is ordered and buffered per trigger

• Shipped to CIC via redundant serial link

• Has to be low-noise, rad-hard

Crate Interface Card

CIC provides interface to DAQ system

• Each card collects data from 8 microcrates • 12 cards per crate

• 2 DAQ interfaces per crate

• Commercial microprocessor and memory

FMUX/FETX Prototype Development

Prototypes implemented in NT 1.2μ CMOS process

• Most aggressive technology available through CMC

• Cost-effective and well-supported

• Final design will be transferred to rad-hard process

First designed a low-level differential receiver and driver

• Basic circuit designed by J. Van Der Spiegel

• Second iteration being submitted 20/1/93

First prototype submitted for fabrication Sep 1992

• Implemented input interface, on-board FIFO

• Received chips Dec 1992

• Currently under test and evaluation

Short-Term ASIC Development Schedule

Second FMUX prototype design submitted 20/1/93

• Includes FETX and optimised layout

• Receive components in Apr 1993

• Has functionality to work with prototype L2B and SDC portable DAQ

Designing test board for prototype FMUX

• Employs TEM for trigger and clock signals

• Mezzanine architecture to allow tests of several circuits • Confronting issues of clock distribution, slow control

• Expect to have design complete by Feb 1993

Long-Term Schedule

Have following milestones for DCC

Jan 1993  Submit 2nd FMUX/FETX prototype
Feb 1993  Complete test board for L2B/FMUX/FETX
Apr 1993  Receive FMUX/FETX prototype from CMC
Jun 1993  System test of L2B/FMUX/FETX
Sep 1993  Design of prototype CIC
Nov 1993  Fabrication of prototype CIC complete
Jan 1994  System test of TMC/L2B/FMUX/FETX/CIC
Apr 1994  SDC Design Review
May 1994  Submit design of production prototype FMUX/FETX
Jun 1994  Begin assembly of production prototype CIC
Sep 1994  Production prototypes evaluated
Oct 1994  Commence production
Sep 1995  Production complete
Dec 1995  Begin installation and testing at SSCL

Cost Estimate

Costing performed using DOE guidelines and SDC WBS

• Estimated engineering and technical effort

• No contingencies in these costs (but 20% assumed)

Summary of Straw Tube Electronics

• Preliminary simulation work on DCC now complete

• Design / fabrication of prototype ASIC’s underway

• Currently testing initial prototypes

• System test of L2B/FMUX/FETX Jun 1993

• Prototype CIC for Jan 1994

FCAL Electronics and DAQ

Plan to read out FCAL using central calorimeter electronics

• High-speed ADC will digitize at each crossing

• Data stored locally till L2 decision

• 20-bit dynamic range

• Costed at ∼ $100 / channel

• US Collaborators responsible for R&D of FE

IPP responsible for packaging of FE and DCC system

• Relative scale of system is modest

• Instrument ∼ 4000 channels

• Overall read out architecture identical with central calorimeter

Proposed FCAL Electronics R&D

Work on FCAL FE electronics will being summer 1993

• Use Central Calorimeter Digital Storage and Readout Card • Decide on packaging and necessary trigger signals

Resources required for next year are modest

• ∼ 1 man-month of design

• SDC portable DAQ for readout of Prototype HADCAL