Data Collection Circuit for the

SDC Straw Tube Tracker

G. Stairs, A. Hölscher, P. Sinervo University of Toronto, Toronto, M5S 1A7

K. Ragan, K.Strahl

McGill University, Montréal, H3A 2T8

1. Introduction

2. Data Collection Circuit Architecture 3. Status of the FMUX-ASIC

4. CIC Design

5. Control Issues

6. Conclusions

KEK SDC Meeting May 1993

Overview of Straw Tube Electronics

SDC baseline design includes a straw tube outer tracker

• Has ∼ 140, 000 individual straw tunes

• Must measure drift time to ∼ 1 ns accuracy

• Allow multiple hits/tube/interaction

Baseline design consists of

• Amplifier-Shaper-Discriminator circuit

• Time Memory Cell to digitize and hold data for L1 decision • Level 2 Buffer to hold digital data for L2 decision

• Data Collection Circuit to move date to DAQ system

Data Collection Circuit

Tasks of the DCC (Data Collection System)

• Has to multiplex the data from 140,000 straw tubes and direct them to DAQ

• DCC has error handling and monitor functions

• System has to sustain datarates for L2 accept rates of up to 10 kHz.

Scale of the “Problem”

140,000 × 10% × 4 bytes × 10 kHz = 5 Gbit/s

This rate is a pessimistic estimate

• lower L2 accept rate

• lower multiplicities at design luminosity

• data compaction schemes

Straw Tube Occupancies

Estimates have been made of straw tube occupancies

• SDCSIM results for Higgs production (solid)

• dijet events (dashed)

• Included 5 minimum bias events (3 × 1033 cm−2s−1 )

• Readout arranged in “modules”

Superlayer Number

Detailed Buffering Studies

A number of groups have performed detailed studies of data collection strategies:

• Illinois has been developing a complete DAQ model

• SSC has studied alternative strategies for DCC control

We chose a data-driven scheme to collect the data

• FE Electronics automatically sparsifies

• Less control logic is required

• Each level in data collection scheme is independent

General DCC Architecture

The DCC system has two “levels” of data collection:

1. multiplexor adjacent to L1/L2 buffers in microcrate

• avoid noise generation: differential signals with 150 mV full swing ⇒ develop special driver/receivers.

• ASIC required: FMUX (Front End Multiplexer)

2. collector located in standard DAQ crate outside the calorimeter

• implemented in standard digital logic

• 96 Crate Interface Cards (CIC)

• Ship the Data to the DAQ via 16 1 Gps optical fibre links

FMUX-ASIC (Front End Multiplexer)

FMUX prototype being developed in Bell Northern Telecom 1.2 μm CMOS process

• Each microcrate is read out by 5 or 7 FMUX ASIC’s

• Each FMUX reads out 8 TMC’s, 32 data channels in total, over serial lines.

• Data stored in 24 bit × 16 FIFO

• Three FMUX’s have serial links to the CIC → can switch datapath between a FMUX and CIC.

• Data transmitted using 4→5 bit group-encoding to CIC.

• Datum from TMC/L2B is 24 bits long.

FMUX adds 8 bit geographical address

FMUX Data Word Organisation

Bits  Function  Dummy Value
0-7  Fine timing data  00000000
8-9  Bunch Counter  00
10-11  Channel ID  Channel ID
12-15  error/flag field  0000
16-23  L1ID  L1ID

Further data compaction takes place in CIC

• packets are created

• data validation and compression can be performed • can be handled by 1 RISC processor/2 microcrates

FMUX-L2B Interface

The FMUX-L2B interface is controlled by 6 lines:

Line Name  L2B FMUX  Function
Data_{0}  OUT  IN  Data
Data_{1}  OUT  IN  Data
Data_{2}  OUT  IN  Data
Data_{3}  OUT  IN  Data
Cdata V alid OUT  IN  Ready to send signal
RClk  IN  OUT  Data Clock

Serial readout has several advantages

• Can be clocked slowly (1-2 MHz)

• Six nibbles at 2 MHz ⇒ 3 μs per datum

• Failure of TMC/L2B or interconnections only disables 4 channels

FMUX-CIC Interface

Data transmission from FMUX to CIC is over 1-bit serial link

• Data are 4 → 5 bit Group-encoded

• Self-synchronizing through use of data frames

• Robust and efficient scheme

• Redundant link (3 channels per microcrate)

Group Data Value  Control  Comment
00000  Fa  Frame group a
00001  Illegal
00010  Illegal
00100  0000
00101  0001
00111  0010
01010  Sa  Idle group a
10101  Sb  Idle group b
01111  Illegal
11000  Illegal
11111  Fb  Frame group b

Overall Control of Readout

System designed so that readout is event and channel ordered Channel Ordering

• easily implemented in FMUX readout by reading each FMUX out one after the other

• FMUX’s are chained together and pass “token”

Event Ordering

• Low Luminosity: Easy - only one event in readout pipeline • High Luminosity: More difficult - several events in pipeline.

• Requires a signal from TMC/L2B to FMUX that all data

for a given trigger has been transfered Solution is to have L2B send one End Of Datum (EOD) datum at the end of each event

EOD: 0000 0000 0000 1010 L1ID L1ID

FMUX uses EOD to signal when all data for event is available

Error Detection and Recovery

A number of exceptional “error” conditions can occur

• Buffers fill up (due to bottleneck downstream?) but trigger continues to generate L2 accepts

– FMUX cannot accept more data

– TMC/L2B must count number of L2 accepts “piling up”

– generate appropriate number of EOD’s when dataflow commences

• Other exceptional conditions are “flagged” by inserting datum into data stream with status code

– CIC can collect and monitor these

– Signal via slow control system when rate of errors is not tolerable

• Could use some form of Boundary Scan for additional control at L2B and FMUX level if SDC ever agrees on a coherent implementation

Alternative Models for L2B Readout

Are also considering alternative option of bus-based FMUX

• Would have to provide similar functionality

• Need interface between L2B and bus

• Most of FMUX-FETX functionality still necessary

Primary concerns are

• Reliability and fault-tolerance

• Open questions on noise and slow control

Crate Interface Card

Data from the each microcrate “pushed” to CIC card

• Each CIC reads out 8 microcrates using 4 RISC CPU’s • Each CPU (Crate Input Processor or CIP) captures data

from two microcrates

– performs data validation

– strips redundant information (L1ID’s for example)

– could check data quality

– generates one data packet for each event

• Data packets shipped to DAQ via interface in crate

• Data rates barely manageable over crate backplane – Considering point-to-point connections to DAQ

– This is currently under discussion with DAQ people

CIC has various tasks apart from data collection

• Error recovery and monitoring

• Provide distribution of slow control signals

• Provide HV distribution for straw modules

• Datapath for trigger tracking data

Internal Structure of CIC

CIC divided into four Crate Input Processors

• Each handle data from two modules

• An input ASIC or DSP moves data into DRAM

• RISC monitors dataflow and data compression

• Output ASIC or DSP moves data to DAQ

Design “shifting” as DAQ protocols and crates change

Prototype Development

Received 2 channel FMUX/FETX prototype

• Fabricating “test” VME fixture

• Bringing up Portable DAQ and TEM

• Plan to interface to L2I and TMC this summer

• Will have a number of chips

provided current prototype works

Next milestone is prototype CIC design

• Will implement in standard VME

• Will provide readout for at least two modules

• Currently working on functional layout and modeling

Summary and Outlook

• Have developed architecture for SDC outer tracker

– Two levels of data collection

– Designed for redundancy and fault-tolerance

– Can sustain an L2 accept rate of up to 10 kHz

– Verilog simulations show that buffer and band-

width requirements are managable

• First FMUX ASIC prototype now being tested

• Preparing test stand for use with SDC portable DAQ and Trigger Emulation Module

• Plan to do a detailed fault-tolerance analysis

• CIC layout should be complete by fall 1993

• Full system prototype by late 1993 or early 1994